The present invention relates, in general, to semiconductor devices and, more particularly, to power Metal Oxide Semiconductor Field Effect Transistors (MOSFETs).
Power MOSFETs have been used in applications requiring high currents and high blocking voltages. Power MOSFETs provide a fast current switching response, a high input impedance, and high thermal stability and are applicable in systems such as Direct Current (DC) converters, motor control circuits, cellular phones, power supplies, and automotive switching circuits. A disadvantage of power MOSFETs is the on-resistance of the transistor that causes a drain-to-source voltage drop when the transistor is conducting high currents.
Efforts have been made to reduce the cell area of the power MOSFET and lower the on-resistance of the transistor. However, power MOSFETs having the gate and channel extending horizontally along the top surface of the semiconductor substrate are limited by the presence of a parasitic Junction Field Effect Transistor (JFET) between adjacent cells. The parasitic JFET increases the on-resistance of the power MOSFET as the device structure is scaled to smaller cell sizes.
To avoid this limitation inherent in the structure of the horizontal power MOSFET, a gate and conduction channel are formed vertically along a trench etched in the semiconductor substrate. The vertical orientation of the trench allows scaling of the gate and channel to reduced sizes without the effects of the parasitic JFET. Thus, the vertical orientation of the power MOSFET reduces the on-resistance when the power MOSFET is in the conduction mode.
Accordingly, it would be advantageous to form a vertical power MOSFET using a fabrication method that uses existing lithography equipment and is easily and inexpensively manufactured. It would be of further advantage to provide a power transistor having a low on-resistance when the power MOSFET is in the conduction mode.